1. Field of the Invention
The present invention relates to a semiconductor memory device. For example, the present invention relates to a semiconductor memory including MOS transistors each having a floating gate and a control gate.
2. Description of the Related Art
NOR type flash memories and NAND type flash memories have been known and widely used as nonvolatile semiconductor memories. In recent years, a flash memory having the advantages of both NOR type flash memory and NAND type flash memory has been proposed in, for example, Wei-Hua Liu, “A2-Transistor Source-select (2TS) Flash EEPROM for 1.8 V-Only Application”, Non-Volatile Semiconductor Memory Workshop 4.1, 1997 (this flash memory is hereinafter referred to as a 2Tr flash memory).
The recent flash memories have been increasingly scaled down. For example, inter-bit-line distance has been reduced. Thus, memory cells are likely to be affected by micro-defects such as dust which may occur between wires during a manufacturing process.
Accordingly, before memories are shipped as products, the memory cells need to be subjected to stress tests. The stress test involves, for example, applying a voltage to between adjacent bit lines or between a bit line and an adjacent source line to check whether or not the memory cell operates correctly. If any defect is occurring, for example, dust is present between the wires, which are thus short circuited, the corresponding memory cell is determined to be defective. An appropriate measure is then taken for this memory cell; it is replaced with a redundant memory cell.
However, the conventional stress test must be conducted for each even-numbered bit line and each odd-numbered bit line or for each even-numbered source line and each odd-numbered source line. This increase the time and cost required for the tests.